1. Field of the Invention
The present invention relates to digital data transmissions exchanged between integrated circuits, using bidirectional two-way CMOS links tailored for reception and transmission.
2. Description of Related Art
As the amount of data exchanged between a very great number of processors increases, links tailored for transmitting these data from one end of the link to the other while guaranteeing their integrity are increasingly needed.
For high outputs, that is, high frequencies, the inductance and the capacitance of the transmission medium must be taken into account; the effects of this medium mean that the variations in potential are propagated in the form of progressive waves along the medium.
The speed of propagation of this wave on a line is a function of the inductance and capacitance of the line, which then define the characteristic impedance of the line.
Any variation in impedance or maladaptation causes a variation in the speed of propagation of the wave, which then breaks down into a transmitted wave and a reflected wave, which can interfere with one another and lead to a partial or total loss of the information exchanged over the line.
To prevent this phenomenon, the line is made to have a structure and hence a characteristic impedance that are constant over its entire length.
However, it is difficult to prevent the phenomena of maladaptation, which are associated particularly with different branches of the line, and especially with the connections of the processors along the line.
In general, a bidirectional transmission requires the presence of a buffer state which is both a transmitter and a receiver, also called a bidirectional buffer, at the level of each processor, the buffer being coupled to the transmission line by an adaptation impedance.
The transmission line, while being so tailored, can still have certain imperfections.
The direction of transmission must be capable of being bidirectional; that is, under the control of a predetermined control signal, each end of the link can be a receiver at some times and a transmitter at others.
One can choose to make bidirectional transmissions simultaneously in both directions or not, but the option of simultaneous transmission requires buffers of extremely delicate design, which are capable of separating the transmitted data from the received data.
A link of the GTL type (for xe2x80x9cGunning Transceiver Logicxe2x80x9d) that is designed specifically to make multi-way transmissions and thus to be capable of managing two-way bidirectional transmissions. This type of link is defined by the JEDEC standard and is the subject of U.S. Pat. No. 5,023,488, entitled xe2x80x9cDrivers and Receivers for Interfacing VLSI CMOS Circuits to Transmission Linesxe2x80x9d.
However, although this solution is well suited to multi-way transmissions, nevertheless it is hard to use for two-way links. In particular, it has the disadvantage of not using the full capacities of the GTL intended for managing the multi-way links, while also having to manage the disadvantages.
These disadvantages are, in particular, elevated currents and current peaks, a specific power supply, and a reference voltage to be generated and distributed.
Adaptation devices based on high-precision, adjustable-value resistance connector bars disposed outside of packages are also known. These connector bars are relatively bulky on boards or cards, whose already-limited dimensions support an ever-increasing number of processors.
Integrated circuits including one or more conductances adjusted to a set-point value are known. Integrating conductances with the integrated circuit allows great economy in terms of space and reduces the problem of connections.
One such circuit is described in particular in French Patent 2 730 365, and entitled xe2x80x9cCircuit integrxc3xa9 avec conductance rxc3xa9glable xc3xa1 partir d""un signal numxc3xa9rique de commandedxe2x80x9d and its U.S. Pat. No. 5,652,538 [Integrated circuit with adjustable conductance based on a digital control signal]. This reference describes an integrated circuit that includes at least one conductance that can be adjusted on the basis of a digital set-point signal that encodes value increments for rendering an exact value as discrete with a relatively fixed precision. The conductance comprises elementary conductances that each define one value increment, such that each elementary conductance is dimensioned so that two successive value increments of the digital set-point signal correspond to a single value increment of the conductance. If the first of the two value increments of the digital set-point signal is a value that is less, or greater, than the exact value, then the corresponding elementary conductance is activated or deactivated, respectively. Thus the total adjusted conductance value is equal to the exact value, with the same relative precision, without oscillating between two values on either side of this exact value.
This type of solution requires complex logic for processing a set-point signal that makes it possible to control the conductances used for adaptation of the integrated circuit. This control logic is relatively difficult to use and not insignificantly increases the size of the integrated circuit that receives these adaptation conductances.
One object of the present invention is to obtain performance equivalent to that obtained with a GTL-type link for transmitting data in the first xe2x80x9coutbound legxe2x80x9d of the signals, without waiting for a xe2x80x9cround tripxe2x80x9d on the line, while having less of an impact on the environment in terms of electrical currents, power supplies, and packaging.
To this end, the first subject of the invention is a bidirectional two-way CMOS link of the type including a tailored transmission line connecting two integrated circuits to its two ends, these integrated circuits respectively including a transceiver that includes a transmitter stage and a receiver stage, interfacing with the line and controlled to transmit or receive digital data exchanged over the transmission line as a function of a control signal to put it in either the transmission mode or the reception mode, the transceivers never being in the same mode at the same time.
According to the invention, the link is characterized in that each transceiver includes at least one NMOS transistor and one PMOS transistor, which are controlled respectively by the control signal and are dimensioned and arranged to adapt the link to the two ends of the transmission line.
In one characteristic, the NMOS and PMOS transistors are dimensioned and arranged to behave like adaptation resistors, in the reception mode.
According to another characteristic, the adaptation resistors have parabolic characteristics, and that their algebraic sum defines a quasi-linear characteristic, whose slope is substantially equal to the characteristic impedance value of the transmission line.
The invention has the advantage in particular of dampening the effects due to the package from the standpoint of the receiver, and of using the transistors of the buffers, implanted in the integrated circuit, to perform the adaptation of the link while reducing the number and size of the MOS transistors.
The invention does not use particular control signals; instead, it uses only the validation signals of the transceivers of the integrated circuits.
Another advantage is that there is no need for external resistors, which makes for a lower cost and thus makes it easier to design the printed card.
This advantage is far from negligible and can even become primary, given the hundreds of links, or even more than a thousand links, based on the same package.
Another advantage of integrated adaptation resistors according to the invention is that if the production variation is such that the PMOS and NMOS transistors have a range of variation that matches a perfectly centered technology, then the direction of variation of the Thxc3xa9venin voltage generator, which is equivalent to integrated resistors, varies in the same direction as the triggering voltage of the inverter used as an input director. Hence there is at least partial compensation for the variations.
Finally, implanting terminal resistors RT in the integrated circuit provides the best attenuation of the parasitic oscillations induced by the maladaptations caused by the package connectors.